This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Memory compilers take user configuration and assemble tile-cells to generate a memory instance. Traditional memory compilers are built by mining characterized data for hundreds of memory instances to cover an entire memory compiler space. Data for a memory instance is typically calculated as a sum of individual tile-cells. However, the tile-cells have different placement in different memory instances, which may result in different charge/discharge paths, resistance-capacitance (RC), etc. Unfortunately, this traditional technique may introduce accuracy errors in memory instance data. Sometimes leakage, timing, power and noise data for hundreds of instances is stored, and a memory compiler analyzes hundreds of instances with semi-automatic vectors related to the entire memory circuit, gathers results and computes a final result. However, this technique is costly, time consuming and inefficient. These techniques can cause accuracy errors because some tile-cells are sensitive to a number of rows (e.g., bitcells, columns, and wordline drivers).